A Phase Locked Loop (PLL) is used to control the phase an oscillator. The PLL was first disclosed in France in 1931, and subsequently in U.S. Pat. No. 1,990,428 to Henri de Bellescize which described controlling the phase of a local oscillator by comparing it to a reference incoming oscillator phase to produce an error signal proportional to the phase difference ΔΨ, and using a narrow, large time constant filter to apply the phase error signal to the local oscillator to be corrected. The '428 patent further observed that so long as the oscillators were close in frequency, the two oscillations automatically maintain a fixed phase relation or phase difference.
U.S. Pat. Nos. 3,217,267 and 3,353,104 to Loposer, circa 1965, introduced the concept of using a digitally controlled divider in the feedback path of the PLL. Loposer observed that the output of the variable frequency oscillator is divided down to the reference frequency and phase-lock is achieved at this lower frequency. This approach is advantageous because selective frequency multipliers are not achievable, while selective dividers are. That is to say, when frequencies are multiplied, there is obtained not one multiple of the input frequency as an output but rather all multiples. In other words Loposer's improvement over the prior art was to easily be able to control the ratio of the output frequency to the reference frequency to an integer. Loposer's Integer PLL readily provided selective division ratios in integer steps, while maintaining phase lock of the output.
U.S. Pat. No. 4,204,174 to King in 1978 further refined Loposer's Integer PLL by the inclusion of a PLL phase locked loop in which a variable frequency voltage-controlled oscillator feeds a phase comparator via an adjustable divider, in which the VCO frequency can be adjusted in smaller steps than the reference frequency.
The '174 patent also observed that in its Fractional N synthesizer, the phase detector controls the VCO frequency Fo accurately at the desired value and therefore, the output frequency Fo can be changed not only in steps each of which has a minimum value equal to the value of the reference frequency Fr, but also in much smaller increments—by making the instantaneous adjustments to the division factor, i.e. N.
Riley et al. discussed the use of a delta-sigma modulator in a fractional N synthesizer in the 1993 paper entitled “Delta-Sigma Modulation in Fractional N Frequency Synthesis,” IEEE JSSC May 1993. This type of modulation improved the output noise spectra while maintaining the basic phase relationships between the reference and output signals.
Riley described the rational fractional division by N in different terms, where n is the integer part, 2k, the modulus, is the maximum value in the accumulator and K is the desired fractional part:N=n+K/2k  (1)
Riley also pointed out that the accumulator modulus need not be an even power of two, and that exact decimal values could be obtained if a more general modulus M were usedN=n+K/M  (2)
In the paper entitled “A Simplified Continuous Phase Modulator Technique”, IEEE JSSC May 1994, Riley et al. detailed the use of a Fractional N Synthesizer to control the phase of an output waveform and showed how a Fractional N synthesizer could be used to implement narrowband constant-envelope continuous-phase modulation. The continuous phase modulation using a Fractional N Synthesizer, demonstrated by Riley also included the case of a single phase step.
In summary, by 1994, it was understood that the output frequency of a fractional synthesizer, ωo, was given by:ωo=Nωr=(n+K/M)ωr  (3)Where N is a rational number, of the form N=n+K/M, ωr is the reference frequency and ωo is the phase locked output frequency. As time progresses, the output phase is given by the frequency time product plus the initial phase.
It was also understood that if the frequency varies with time then the phase at a given time is defined by the integral of the frequency time product plus the initial value. If K is a sequence that varies with time, we can represent the instantaneous division ratio as N(t) and then the phase at any point in time is given by θ(t):Phase=ωot+θi=Nωrt+θi=(n+K/M)ωrt+θi  (4)
                                          θ            o                    ⁡                      (            t            )                          =                              ∫                                          N                ⁡                                  (                  t                  )                                            ⁢                              ω                r                            ⁢                                                          ⁢              dt                                +                      θ            ⁢                                                  ⁢            i                                              (        5        )            
It was also understood that the first accumulator in the delta-sigma modulator integrated the value of N(t), hence represented the instantaneous phase of the output, and that the initial value in the accumulator, or its “seed” value, represented the initial phase of the output oscillator θI.
Stated in terms of the values in the accumulator, the initial output phase is given by initial value Ni in the phase accumulator, scaled by 2π/MθI=2πNi/M  (6)
U.S. Pat. No. 7,463,710 to Walsh et al. relates to a synthesizer that can program the output phase of a VCO at ωo, when the output frequency is related to ωr by the relationship below, where the modulus of the accumulator is M, an integer, related to the desired step size of the synthesizer.ωo=n+K/Mωr  (7)
Since the phase of the output is dependent upon the initial value in the accumulator (referred to as an interpolator by the '710 patent), the phase in the future is given by (5) and hence if one wishes to return to the same phase at some time in the future, one needs to recall the product of time and frequency and the seed value.
The synthesizer of the '710 patent further requires that the output frequency be related to the modulus of the accumulator M, and that the time need only be remembered with an effective period of 2πM/ωr. Hence, the reference and the VCO frequencies of the '710 synthesizer must be related by the modulus of the accumulator. The problem with this method is that the modulus of the frequency must be related to the desired frequency spacing between channels. Not only does this restrict the possible answers, it results in large spurious content in the fractional synthesizer output at the desired channel spacing.